A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system.
Yong-Ha ParkSeon-Ho HanJung-Hwan LeeHoi-Jun YooPublished in: IEEE J. Solid State Circuits (2001)
Keyphrases
- low power
- high speed
- random access memory
- multimedia
- logic circuits
- image sensor
- delay insensitive
- power consumption
- low voltage
- cmos technology
- low cost
- focal plane
- power dissipation
- single chip
- analog to digital converter
- embedded systems
- design considerations
- digital signal processing
- nm technology
- vlsi circuits
- high power
- wireless transmission
- real time
- mixed signal
- low power consumption
- ultra low power
- cmos image sensor
- main memory
- memory access
- vlsi architecture
- solid state
- gate array
- power reduction
- video data
- operating system
- hardware and software
- wide dynamic range
- signal processor
- flash memory