A hardware efficient implementation of an adaptive subsample delay estimator.
Douglas L. MaskellGraham S. WoodsAndrew KeransPublished in: ISCAS (3) (2004)
Keyphrases
- efficient implementation
- hardware implementation
- highly parallel
- low cost
- real time
- hardware and software
- parallel architectures
- maximum likelihood
- random sampling
- active set
- hardware architecture
- efficient processing
- least squares
- computer systems
- graphics processing units
- hardware design
- neural network
- embedded systems
- maximum a posteriori
- parallel algorithm
- estimation error
- field programmable gate array