High speed CRC with 64-bit generator polynomial on an FPGA.

Amila Akagic Hideharu Amano

Published in: SIGARCH Comput. Archit. News (2011)

Keyphrases

high speed
shift register
low power
galois field
pseudorandom
s box
data acquisition
high speed networks
real time
xilinx virtex
neural network
hardware architecture
bit parallel
polynomial hierarchy
polynomial equations
frame rate
cellular automata
data sets