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Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic.

Avadhoot KhairnarBhavuk ChauhanGeetanjali SharmaAmit M. Joshi
Published in: J. Circuits Syst. Comput. (2022)
Keyphrases
  • bit parallel
  • hybrid learning
  • logic circuits
  • pattern matching
  • single chip
  • chip design
  • database
  • low power
  • design methodology