Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.

Michael Zhang Krste Asanovic

Published in: ISCA (2005)

Keyphrases

multithreading
power dissipation
high speed
phase locked loop
low cost
fault tolerant
data partitioning
high density
distributed databases
parallel implementation
fault tolerance
neural network
analog vlsi
real time
data replication
vlsi implementation
wireless link
programmable logic