A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier.
Yong-Suk ChoJae Yeon ChoiPublished in: FGIT-GDC/IESH/CGAG (2012)
Keyphrases
- hardware implementation
- parallel architecture
- bit parallel
- processing elements
- efficient implementation
- software implementation
- signal processing
- pipelined architecture
- shift register
- hardware design
- co occurrence
- dedicated hardware
- field programmable gate array
- pipeline architecture
- fpga implementation
- hardware architecture
- image processing algorithms
- parallel implementation
- image binarization
- shared memory
- fpga device
- xilinx virtex
- massively parallel
- memory management
- real time
- parallel programming
- parallel computation
- parallel processing
- computer architecture