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Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design.
Anjali Sharma
Harsh Sohal
Harsimran Jit Kaur
Published in:
J. Circuits Syst. Comput. (2019)
Keyphrases
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high speed
circuit design
low power
power consumption
real time
design automation
lightweight
cost effective
computationally expensive
power dissipation
data structure
signal processing
focal plane
high speed networks