Head-of-Line Blocking Avoidance in Networks-on-Chip.

José V. Escamilla Jose Flich Pedro Javier García

Published in: IPDPS Workshops (2013)

Keyphrases

input output
high bandwidth
high speed
low cost
record linkage
social networks
network design
complex networks
network size
head pose estimation
real time
high density
power law
network model
analog vlsi
single chip
circuit design
low power
computer networks
network structure
data sets