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2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS.

Barend van LiempdBenjamin P. HershbergKuba RaczkowskiSaneaki AriumiUdo KarthausKarl-Frederik BinkJan Craninckx
Published in: ISSCC (2015)
Keyphrases
  • low voltage
  • database
  • circuit design
  • analog vlsi