A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS.

Jan Craninckx Michiel S. J. Steyaert

Published in: IEEE J. Solid State Circuits (1996)

Keyphrases

high speed
power consumption
low cost
low power
blind equalization algorithm
primal dual
circuit design
power supply
focal plane
analog vlsi
hd video
data sets
genetic algorithm
dual formulation
delay insensitive