Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology.

Ming-Dou Ker Jeng-Jie Peng

Published in: CICC (1998)

Keyphrases

layout design
low power
cmos technology
inter cell
model checking
spl times
mixed signal
low voltage
power consumption
computer vision
moving objects
low cost
high speed