Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches.
Ignatius BezzamShoba KrishnanPublished in: VLSI Design (2014)
Keyphrases
- power dissipation
- low power
- power consumption
- low cost
- high speed
- vlsi circuits
- single chip
- chip design
- data driven
- gate array
- digital signal processing
- information gain
- hardware and software
- circuit design
- signal processing
- vlsi architecture
- real time
- pattern recognition
- data structure
- objective function
- knowledge base
- neural network