Low-power network-on-chip for high-performance SoC design.

Kangmin Lee Se-Joong Lee Hoi-Jun Yoo

Published in: IEEE Trans. Very Large Scale Integr. Syst. (2006)

Keyphrases

low power
low power consumption
power dissipation
single chip
power consumption
low cost
cmos technology
high speed
vlsi architecture
logic circuits
network on chip
digital signal processing
gate array
mixed signal
signal processor
power reduction
ultra low power
embedded systems
real time
routing algorithm