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Yuanwen Huang
ORCID
Publication Activity (10 Years)
Years Active: 2015-2020
Publications (10 Years): 10
Top Topics
Buffer Overflow
Dynamic Reconfiguration
Symbolic Execution
Embedded Systems
Top Venues
ISQED
ACM Trans. Embed. Comput. Syst.
VLSI-SoC
ICCD
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Publications
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Yuanwen Huang
,
Prabhat Mishra
Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches.
ISQED
(2020)
Alif Ahmed
,
Yuanwen Huang
,
Prabhat Mishra
Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization.
ACM Trans. Embed. Comput. Syst.
18 (2) (2019)
Yuanwen Huang
,
Prabhat Mishra
Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
38 (5) (2019)
Jonathan Cruz
,
Yuanwen Huang
,
Prabhat Mishra
,
Swarup Bhunia
An automated configurable Trojan insertion framework for dynamic trust benchmarks.
DATE
(2018)
Yuanwen Huang
,
Swarup Bhunia
,
Prabhat Mishra
Scalable Test Generation for Trojan Detection Using Side Channel Analysis.
IEEE Trans. Inf. Forensics Secur.
13 (11) (2018)
Yuanwen Huang
,
Prabhat Mishra
Trace Buffer Attack on the AES Cipher.
J. Hardw. Syst. Secur.
1 (1) (2017)
Yuanwen Huang
,
Prabhat Mishra
Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems.
ICCD
(2017)
Farimah Farahmandi
,
Yuanwen Huang
,
Prabhat Mishra
Trojan localization using symbolic algebra.
ASP-DAC
(2017)
Yuanwen Huang
,
Prabhat Mishra
Reliability and energy-aware cache reconfiguration for embedded systems.
ISQED
(2016)
Yuanwen Huang
,
Swarup Bhunia
,
Prabhat Mishra
MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection.
CCS
(2016)
Yuanwen Huang
,
Anupam Chattopadhyay
,
Prabhat Mishra
Trace Buffer Attack: Security versus observability study in post-silicon debug.
VLSI-SoC
(2015)