Vera Pantelic

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 26

Top Topics

Subsumption Architecture

Software Engineering Practices

Autonomous Vehicles

Impact Analysis

Top Venues

SAFECOMP Workshops

ESEC/SIGSOFT FSE

Publications

Federico Formica, Tony Fan, Akshay Rajhans, Vera Pantelic, Mark Lawford, Claudio Menghi
Simulation-Based Testing of Simulink Models With Test Sequence and Test Assessment Blocks. IEEE Trans. Software Eng. 50 (2) (2024)
Stefan Ramdhan, Winnie Trandinh, Sathurshan Arulmohan, Xiayong Hu, Spencer Deevy, Victor Bandur, Vera Pantelic, Mark Lawford, Alan Wassyng
Simulation-based Analysis of a Novel Loop-based Road Topology for Autonomous Vehicles. CoRR (2024)
Stefan Ramdhan, Winnie Trandinh, Sathurshan Arulmohan, Xiayong Hu, Spencer Deevy, Victor Bandur, Vera Pantelic, Mark Lawford, Alan Wassyng
Simulation-based Analysis of a Novel Loop-based Road Topology for Autonomous Vehicles. IV (2024)
Horacio Hoyos Rodriguez, Naveen Ganesh Muralidharan, Faezeh Siavashi, Vera Pantelic, Victor Bandur, Mark Lawford, Richard F. Paige
An Automotive Architecture Product Line for E/E Powertrain Architectures. MoDELS (Companion) (2023)
Faezeh Siavashi, Horacio Hoyos Rodriguez, Vera Pantelic, Mark Lawford, Richard F. Paige, Monika Jaskolka, Guanrui Hou, Alessandro Verde
Bridging the Gap Between System Architecture and Software Design using Model Transformation. ISSREW (2023)
Federico Formica, Nicholas Petrunti, Lucas Bruck, Vera Pantelic, Mark Lawford, Claudio Menghi
Test Case Generation for Drivability Requirements of an Automotive Cruise Controller: An Experience with an Industrial Simulator. ESEC/SIGSOFT FSE (2023)
Federico Formica, Nicholas Petrunti, Lucas Bruck, Vera Pantelic, Mark Lawford, Claudio Menghi
Test Case Generation for Drivability Requirements of an Automotive Cruise Controller: An Experience with an Industrial Simulator. CoRR (2023)
Monika Jaskolka, Vera Pantelic, Alan Wassyng, Richard F. Paige, Mark Lawford
Repository mining for changes in Simulink and Stateflow models. Softw. Syst. Model. 22 (5) (2023)
Ryan Kapinski, Vera Pantelic, Victor Bandur, Alan Wassyng, Mark Lawford
Assurance Cases for Timing Properties of Automotive TSN Networks. SAFECOMP Workshops (2023)
Victor Bandur, Mark Lawford, Sébastien Mosser, Richard F. Paige, Vera Pantelic, Alan Wassyng
Using Assurance Cases to Prevent Malicious Behaviour from Targeting Safety Vulnerabilities. SAFECOMP Workshops (2023)
Federico Formica, Tony Fan, Akshay Rajhans, Vera Pantelic, Mark Lawford, Claudio Menghi
Simulation-based Testing of Simulink Models with Test Sequence and Test Assessment Blocks. CoRR (2022)
Naveen Ganesh Muralidharan, Vera Pantelic, Victor Bandur, Richard F. Paige
Integrating Software Issue Tracking and Traceability Models. ICSME (2022)
Monika Jaskolka, Vera Pantelic, Alan Wassyng, Mark Lawford, Richard F. Paige
Repository Mining for Changes in Simulink Models. MoDELS (2021)
Victor Bandur, Vera Pantelic, Timofey Tomashevskiy, Mark Lawford
A Safety Architecture for Centralized E/E Architectures. DSN Workshops (2021)
Victor Bandur, Gehan M. K. Selim, Vera Pantelic, Mark Lawford
Making the Case for Centralized Automotive E/E Architectures. IEEE Trans. Veh. Technol. 70 (2) (2021)
Monika Jaskolka, Vera Pantelic, Alan Wassyng, Mark Lawford
Supporting Modularity in Simulink Models. CoRR (2020)
Bennett Mackenzie, Vera Pantelic, Gordon Marks, Stephen Wynn-Williams, Gehan M. K. Selim, Mark Lawford, Alan Wassyng, Moustapha Diab, Feisel Weslati
Change impact analysis in Simulink designs of embedded systems. ESEC/SIGSOFT FSE (2020)
Monika Jaskolka, Stephen Scott, Vera Pantelic, Alan Wassyng, Mark Lawford
Applying Modular Decomposition in Simulink. ISSRE Workshops (2020)
Vera Pantelic, Alexander Schaap, Alan Wassyng, Victor Bandur, Mark Lawford
Something is Rotten in the State of Documenting Simulink Models. MODELSWARD (2019)
Stephen Wynn-Williams, Zinovy Diskin, Vera Pantelic, Mark Lawford, Gehan M. K. Selim, Curtis Milo, Moustapha Diab, Feisel Weslati
SL2SF: Refactoring Simulink to Stateflow. FASE (2019)
Alexander Schaap, Gordon Marks, Vera Pantelic, Mark Lawford, Gehan M. K. Selim, Alan Wassyng, Lucian M. Patcas
Documenting Simulink designs of embedded systems. MoDELS (Companion) (2018)
Vera Pantelic, Steven M. Postma, Mark Lawford, Monika Jaskolka, Bennett Mackenzie, Alexandre Korobkine, Marc Bender, Jeff Ong, Gordon Marks, Alan Wassyng
Software engineering practices and Simulink: bridging the gap. Int. J. Softw. Tools Technol. Transf. 20 (1) (2018)
Archana Mallya, Vera Pantelic, Morayo Adedjouma, Mark Lawford, Alan Wassyng
Using STPA in an ISO 26262 Compliant Process. SAFECOMP (2016)
Monika Bialy, Mark Lawford, Vera Pantelic, Alan Wassyng
A Methodology for the Simplification of Tabular Designs in Model-Based Development. FormaliSE@ICSE (2015)
Vera Pantelic, Steven M. Postma, Mark Lawford, Alexandre Korobkine, Bennett Mackenzie, Jeff Ong, Marc Bender
A Toolset for Simulink - Improving Software Engineering Practices in Development with Simulink. MODELSWARD (2015)
Marc Bender, Karen Laurin, Mark Lawford, Vera Pantelic, Alexandre Korobkine, Jeff Ong, Bennett Mackenzie, Monika Bialy, Steven M. Postma
Signature required: Making Simulink data flow and interfaces explicit. Sci. Comput. Program. 113 (2015)
Vera Pantelic, Mark Lawford, Steven M. Postma
A Framework for Supervisory Control of Probabilistic Discrete Event Systems. WODES (2014)
Marc Bender, Karen Laurin, Mark Lawford, Jeff Ong, Steven M. Postma, Vera Pantelic
Signature Required - Making Simulink Data Flow and Interfaces Explicit. MODELSWARD (2014)
Vera Pantelic, Mark Lawford
A pseudometric in supervisory control of probabilistic discrete event systems. Discret. Event Dyn. Syst. 22 (4) (2012)
Vera Pantelic, Mark Lawford
Optimal Supervisory Control of Probabilistic Discrete Event Systems. IEEE Trans. Autom. Control. 57 (5) (2012)
Vera Pantelic, Mark Lawford
Use of a metric in supervisory control of probabilistic discrete event systems. WODES (2010)
Vera Pantelic, Steven M. Postma, Mark Lawford
Probabilistic Supervisory Control of Probabilistic Discrete Event Systems. IEEE Trans. Autom. Control. 54 (8) (2009)
Vera Pantelic, Xiao-Hui Jin, Mark Lawford, David Lorge Parnas
Inspection of Concurrent Systems: Combining Tables, Theorem Proving and Model Checking. Software Engineering Research and Practice (2006)
Mark Lawford, Vera Pantelic, Hong Zhang
Towards Integrated Verification of Timed Transition Models. Fundam. Informaticae 70 (1-2) (2006)