Vahid Majidzadeh

Publication Activity (10 Years)

Years Active: 2006-2013
Publications (10 Years): 0

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Joint Source Channel

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Publications

Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding. CICC (2013)
Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici, Jan M. Rabaey
An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements. VLSIC (2012)
Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor. IEEE Trans. Biomed. Circuits Syst. 5 (3) (2011)
Vahid Majidzadeh, Laurent Jacques, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
A (256×256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing. ISCAS (2010)
Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
A fully on-chip LDO voltage regulator for remotely powered cortical implants. ESSCIRC (2009)
Laurent Jacques, Pierre Vandergheynst, Alexandre Bibet, Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
CMOS compressed imaging by Random Convolution. ICASSP (2009)
Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
A micropower neural recording amplifier with improved noise efficiency factor. ECCTD (2009)
Vahid Majidzadeh, Omid Shoaei
A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications. IEICE Trans. Electron. (6) (2006)
Vahid Majidzadeh, Omid Shoaei
A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs. ACM Great Lakes Symposium on VLSI (2006)
Vahid Majidzadeh, Omid Shoaei
Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs. DATE (2006)