Uday Padmanabhan

Publication Activity (10 Years)

Years Active: 2005-2008
Publications (10 Years): 0

Publications

Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design CoRR (2007)
Janet Meiling Wang, Bharat Sukhwani, Uday Padmanabhan, Dongsheng Ma, Kartik Sinha
Simulation and Design of Nanocircuits With Resonant Tunneling Devices. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2007)
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
Statistical clock tree routing for robustness to process variations. ISPD (2006)
Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design. DATE (2005)