T. Vigneswaran

Publication Activity (10 Years)

Years Active: 2014-2020
Publications (10 Years): 9

Top Topics

Response Variable

Regression Model

Finite Impulse Response

Top Venues

Int. J. Adv. Intell. Paradigms

Concurr. Comput. Pract. Exp.

Wirel. Pers. Commun.

Publications

Abraham Sudharson Ponraj, T. Vigneswaran
Daily evapotranspiration prediction using gradient boost regression model for irrigation planning. J. Supercomput. 76 (8) (2020)
M. Jasmin, T. Vigneswaran
An adaptive low power coding scheme for the NoC. Int. J. Adv. Intell. Paradigms 13 (3/4) (2019)
S. Nirmalraj, T. Vigneswaran
Analog to information convertor using cascaded transform and Gaussian random matrix. Clust. Comput. 22 (5) (2019)
S. Umadevi, T. Vigneswaran
Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications. Clust. Comput. 22 (6) (2019)
P. Radhika, T. Vigneswaran, J. Selvakumar
Design of high performance filter bank multi-carrier transmitter. Clust. Comput. 22 (5) (2019)
V. Sarada, T. Vigneswaran, J. Selvakumar
Low-power and high-throughput 128-point feedforward FFT processor. Clust. Comput. 22 (6) (2019)
A. Maria Jossy, T. Vigneswaran, S. Malarvizhi, K. K. Nagarajan
Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method. Concurr. Comput. Pract. Exp. 31 (14) (2019)
S. Beulah Hemalatha, T. Vigneswaran
Reconfigurable communication wrapper for QoS demand for network on chip. Int. J. Adv. Intell. Paradigms 12 (1/2) (2019)
E. Chitra, T. Vigneswaran, S. Malarvizhi
Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic. Wirel. Pers. Commun. 102 (4) (2018)
Amita Nandal, T. Vigneswaran, Ashwani K. Rana
DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic. Circuits Syst. Signal Process. 33 (3) (2014)