Shuu'ichirou Yamamoto

Publication Activity (10 Years)

Years Active: 2009-2021
Publications (10 Years): 5

Top Topics

Metal Oxide Semiconductor

Comparative Study

Top Venues

IEEE Open J. Circuits Syst.

Publications

Hayato Yoshida, Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches. IEEE Open J. Circuits Syst. 2 (2021)
Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions. IEICE Electron. Express 17 (4) (2020)
Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters. NGCAS (2018)
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
Energy performance of nonvolatile power-gating SRAM using SOTB technology. ESSCIRC (2016)
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
Design and implementation of nonvolatile power-gating SRAM using SOTB technology. ISLPED (2016)
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. DATE (2015)
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology. APCCAS (2014)
Ryosho Nakane, Yusuke Shuto, Hiroaki Sukegawa, Zhenchao Wen, Shuu'ichirou Yamamoto, Seiji Mitani, Masaaki Tanaka, Koichiro Inomata, Satoshi Sugahara
Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service. ESSDERC (2013)
Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. CICC (2009)