Süleyman Sirri Demirsoy

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 5

Top Topics

Approximate Pattern Matching

Arithmetic Coding

High Compression Ratio

Data Processing

Top Venues

Publications

Norman May, Daniel Ritter, Andre Dossinger, Christian Faerber, Süleyman Sirri Demirsoy
DASH: Asynchronous Hardware Data Processing Services. CIDR (2023)
Robert Lasch, Mehdi Moghaddamfar, Norman May, Süleyman Sirri Demirsoy, Christian Färber, Kai-Uwe Sattler
Bandwidth-optimal Relational Joins on FPGAs. EDBT (2022)
Robert Lasch, Ismail Oukid, Roman Dementiev, Norman May, Süleyman Sirri Demirsoy, Kai-Uwe Sattler
Faster & strong: string dictionary compression using sampling and fast vectorized decompression. VLDB J. 29 (6) (2020)
Robert Lasch, Süleyman Sirri Demirsoy, Norman May, Veeraraghavan Ramamurthy, Christian Färber, Kai-Uwe Sattler
Accelerating re-pair compression using FPGAs. DaMoN (2020)
Robert Lasch, Ismail Oukid, Roman Dementiev, Norman May, Süleyman Sirri Demirsoy, Kai-Uwe Sattler
Fast & Strong: The Case of Compressed String Dictionaries on Modern CPUs. DaMoN (2019)
Süleyman Sirri Demirsoy, Martin Langhammer
Cholesky decomposition using fused datapath synthesis. FPGA (2009)
Süleyman Sirri Demirsoy, Kellie Marks
SoC framework for FPGA: A case study of LTE PUSCH receiver. SoCC (2009)
Süleyman Sirri Demirsoy
Session MA5: Programmable and reconfigurable architectures. ACSCC (2008)
Ediz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling
A Low-Complexity Self-Calibrating Adaptive Quadrature Receiver. AHS (2006)
Renan Kazazoglu, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling
A computationally efficient DAB bit-stream processor. ISCAS (2006)
Ediz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling
Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers. EUSIPCO (2005)
Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster
Synthesis of reconfigurable multiplier blocks: part I - fundamentals. ISCAS (1) (2005)
Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster
Synthesis of reconfigurable multiplier blocks: part - II algorithm. ISCAS (1) (2005)
Süleyman Sirri Demirsoy, Robert Beck, Andrew G. Dempster, Izzet Kale
Reconfigurable implementation of recursive DCT kernels for reduced quantization noise. ISCAS (4) (2003)
Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale
Design guidelines for reconfigurable multiplier blocks. ISCAS (4) (2003)
Süleyman Sirri Demirsoy, Robert Beck, Izzet Kale, Andrew G. Dempster
New Recursive DCT Implementations with Goertzel filters. Int. J. Comput. 1 (1) (2002)
Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale
Power analysis of multiplier blocks. ISCAS (1) (2002)
Andrew G. Dempster, Süleyman Sirri Demirsoy, Izzet Kale
Designing multiplier blocks with low logic depth. ISCAS (5) (2002)
Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale
Transition analysis on FPGA for multiplier-block based FIR filter structures. ICECS (2000)