Paul T. Hulina

Publication Activity (10 Years)

Years Active: 1970-1999
Publications (10 Years): 0

Publications

David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor
Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. IEEE International Workshop on Rapid System Prototyping (1999)
David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. ICCD (1999)
Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno
Computing in Memory Architectures for Digital Image Processing. MTDT (1999)
Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian
A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. IEEE International Workshop on Rapid System Prototyping (1999)
David L. Landis, Paul T. Hulina
A WWW facilitated rapid system prototyping class. MSE (1997)
Paul T. Hulina, David L. Landis
An electronics manufacturing minor in engineering with emphasis on rapid prototyping. MSE (1997)
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
A comparative evaluation of software techniques to hide memory latency. HICSS (1) (1995)
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
Program Balance and Its Impact on High Performance RISC Architectures. HPCA (1995)
Ali Berrached, Paul T. Hulina, Lee D. Coraor
Structured Data Access Mechanisms for a Decoupled Computer Architecture. ICPP (2) (1994)
Lizyamma Kurian, Bermjae Choi, Paul T. Hulina, Lee D. Coraor
Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. ICPP (1) (1994)
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor
Memory Latency Effects in Decoupled Architectures. IEEE Trans. Computers 43 (10) (1994)
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor
Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. ISCA (1992)
Paul T. Hulina, Lizyamma Kurian, Eugene B. John, Lee D. Coraor
Design and VLSI implementation of an access processor for a decoupled architecture. Microprocess. Microsystems 16 (5) (1992)
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai
Classification and Performance Evaluation of Instruction Buffering Techniques. ISCA (1991)
Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun
Performance Analysis of an Address Generation Coprocessor. ICPP (1) (1991)
Paul T. Hulina, Lee D. Coraor
Coprocessor architectures for efficient address computation and memory accessing. Comput. Syst. Sci. Eng. 5 (3) (1990)
Lee D. Coraor, Paul T. Hulina, Orlando A. Morean
A General Model for Memory-Based Finite-State Machines. IEEE Trans. Computers 36 (2) (1987)
Paul T. Hulina, Lee D. Coraor
A Hardware Memory Mapping Unit for Efficient Address Computation. ICPP (1987)
Lee D. Coraor, Paul T. Hulina
A Reconfigurable Multiprocessor. ICPP (1985)
Jon G. Bredeson, Paul T. Hulina
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops. IEEE Trans. Computers 22 (5) (1973)
Jon G. Bredeson, Paul T. Hulina
Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits Inf. Control. 20 (2) (1972)
Jon G. Bredeson, Paul T. Hulina
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races. IEEE Trans. Computers 20 (2) (1971)
Jon G. Bredeson, Paul T. Hulina
Generation of Prime Implicants by Direct Multiplication. IEEE Trans. Computers 20 (4) (1971)
Jon G. Bredeson, Paul T. Hulina
Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits SWAT (1970)
Paul T. Hulina, Jon G. Bredeson
On Tracey's Internal State Assignment Method. IEEE Trans. Computers 19 (5) (1970)
James L. Elshoff, Paul T. Hulina
The binary floating point digital differential analyzer. AFIPS Fall Joint Computing Conference (1970)