Omar Abdelfattah

Publication Activity (10 Years)

Years Active: 2010-2016
Publications (10 Years): 1

Top Topics

Design Methodology

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Omar Abdelfattah, George Gal, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih
A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih
An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih
A 0.55-V 1-GHz frequency synthesizer PLL for ultra-low-voltage ultra-low-power applications. LASCAS (2015)
Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih
A 0.6V-supply bandgap reference in 65 nm CMOS. NEWCAS (2015)
Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih
A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS. ISCAS (2015)
Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih
Optimization of LC-VCO tuning range under different inductor/varactor losses limitations. CCECE (2014)
Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts
A simple analog CMOS design tool using transistor dimension-independent parameters. ISCAS (2013)
Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts
Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs. NEWCAS (2013)
George Gal, Omar Abdelfattah, Gordon W. Roberts
A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology. MWSCAS (2012)
Omar Abdelfattah, Andraws Swidan, Zeljko Zilic
Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. ICECS (2010)