Minhan Chen

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 4

Top Topics

Clause Learning

Top Venues

Publications

Ping Lu, Minhan Chen, Shaishav Desai
A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC. ISCAS (2024)
Ping Lu, Bupesh Pandita, Minhan Chen
Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface. MWSCAS (2023)
Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak
A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET. ISCAS (2022)
Ping Lu, Minhan Chen, Shaishav Desai
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications. MWSCAS (2022)
Minhan Chen, Wolfgang Porod
. VLSI Design 1998 (1) (1998)