Mateja Putic

Publication Activity (10 Years)

Years Active: 2008-2018
Publications (10 Years): 2

Top Topics

Hierarchical Temporal Memory

Probabilistic Automata

Top Venues

Publications

Mateja Putic, Swagath Venkataramani, Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose, Mircea Stan
Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. DAC (2018)
Mateja Putic, A. J. Varshneya, Mircea R. Stan
Hierarchical Temporal Memory on the Automata Processor. IEEE Micro 37 (1) (2017)
Hang Zhang, Mateja Putic, John C. Lach
Low Power GPGPU Computation with Imprecise Hardware. DAC (2014)
Matthew Weber, Mateja Putic, Hang Zhang, John C. Lach, Jiawei Huang
Balancing Adder for error tolerant applications. ISCAS (2013)
Benton H. Calhoun, Joseph F. Ryan, Sudhanshu Khanna, Mateja Putic, John C. Lach
Flexible Circuits and Architectures for Ultralow Power. Proc. IEEE 98 (2) (2010)
Mateja Putic, Liang Di, Benton H. Calhoun, John C. Lach
Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. ICCD (2009)
Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun
Power switch characterization for fine-grained dynamic voltage scaling. ICCD (2008)