Marcus Vinícius Carvalho da Silva

Publication Activity (10 Years)

Years Active: 2008-2012
Publications (10 Years): 0

Top Topics

Power Consumption

Evolutionary Algorithm

Top Venues

Expert Syst. Appl.

Publications

Nadia Nedjah, Marcus Vinícius Carvalho da Silva, Luiza de Macedo Mourelle
Preference-based multi-objective evolutionary algorithms for power-aware application mapping on NoC platforms. Expert Syst. Appl. 39 (3) (2012)
Nadia Nedjah, Marcus Vinícius Carvalho da Silva, Luiza de Macedo Mourelle
Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization. J. Syst. Archit. 57 (1) (2011)
Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle
Power-Aware Multi-objective Evolutionary Optimization for Application Mapping on NoC Platforms. IEA/AIE (2) (2010)
Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle
Efficient mapping of an image processing application for a network-on-chip based implementation. Int. J. High Perform. Syst. Archit. 2 (1) (2009)
Nadia Nedjah, Rodrigo Martins da Silva, Luiza de Macedo Mourelle, Marcus Vinícius Carvalho da Silva
Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs. Neurocomputing 72 (10-12) (2009)
Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle
Application Synthesis for MPSoCs Implementation Using Multiobjective Optimization. IWANN (1) (2009)
Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle
Evolutionary IP assignment for efficient NoC-based system design using multi-objective optimization. IEEE Congress on Evolutionary Computation (2009)
Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle
Optimal IP Assignment for Efficient NoC-based System Implementation using NSGA-II and MicroGA. Int. J. Comput. Intell. Syst. 2 (2) (2009)
Nadia Nedjah, Rodrigo Martins da Silva, Luiza de Macedo Mourelle, Marcus Vinícius Carvalho da Silva
Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks. ICANN (2) (2008)