Kanji Hirabayashi

Publication Activity (10 Years)

Years Active: 1984-2001
Publications (10 Years): 0

Publications

Kanji Hirabayashi
An Algebraic Approach to Formal Verification of Microprocessors. J. Electron. Test. 17 (6) (2001)
Kanji Hirabayashi
A Method of Formal Verification of Cryptographic Circuits. J. Electron. Test. 13 (3) (1998)
Kanji Hirabayashi
Hazard simulation of sequential circuits. J. Electron. Test. 8 (2) (1996)
Kanji Hirabayashi
A parametric yield model. J. Electron. Test. 6 (3) (1995)
Kanji Hirabayashi
Delay fault simulation of sequential circuits. J. Electron. Test. 4 (2) (1993)
Kanji Hirabayashi
Self-checking CMOS circuits using pass-transistor logic. J. Electron. Test. 2 (2) (1991)
Masahisa Nakazawa, Susumu Nitta, Kanji Hirabayashi
Probabilistic fault grading based on activation checking and observability analysis. J. Electron. Test. 1 (3) (1990)
Susumu Nitta, Masahiko Kawamura, Kanji Hirabayashi
Test generation by activation and defect-drive (TEGAD). Integr. 3 (1) (1985)
Masahiko Kawamura, Kanji Hirabayashi
AFS : An Approximate Fault Simulator. ITC (1985)
Masahiko Kawamura, Haruo Takagi, Kanji Hirabayashi
Functional verification of memory circuits from mask artwork data. DAC (1984)