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Jelle Bailleul
ORCID
Publication Activity (10 Years)
Years Active: 2016-2020
Publications (10 Years): 7
Top Topics
Multipath
Vlsi Design
Communication Systems
Space Time Block
Top Venues
PIMRC
Comput. Electr. Eng.
IEEE Trans. Commun.
IEEE Trans. Wirel. Commun.
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Publications
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Jelle Bailleul
,
Lennert Jacobs
,
Mamoun Guenach
,
Marc Moeneclaey
Optimized Precoded Spatio-Temporal Partial-Response Signaling Over Frequency-Selective MIMO Channels.
IEEE Trans. Wirel. Commun.
19 (9) (2020)
Jelle Bailleul
,
Lennert Jacobs
,
Mamoun Guenach
,
Marc Moeneclaey
Robust Spatio-Temporal Partial-Response Signaling over a Frequency-Selective Fading MIMO Channel with Imperfect CSI.
PIMRC
(2019)
Jelle Bailleul
,
Lennert Jacobs
,
Paolo Manfredi
,
Dries Vande Ginste
,
Mamoun Guenach
,
Marc Moeneclaey
MIMO Time-Domain Equalization for High-Speed Continuous Transmission Under Channel Variability.
IEEE Trans. Commun.
66 (8) (2018)
Lennert Jacobs
,
Jelle Bailleul
,
Paolo Manfredi
,
Mamoun Guenach
,
Dries Vande Ginste
,
Marc Moeneclaey
On Partial Response Signaling for MIMO Equalization on Multi-Gbit/s Electrical Interconnects.
EUSIPCO
(2018)
Lennert Jacobs
,
Jelle Bailleul
,
Paolo Manfredi
,
Mamoun Guenach
,
Dries Vande Ginste
,
Marc Moeneclaey
MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances.
GLOBECOM
(2017)
Jelle Bailleul
,
Lennert Jacobs
,
Paolo Manfredi
,
Dries Vande Ginste
,
Marc Moeneclaey
Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances.
Comput. Electr. Eng.
62 (2017)
Jelle Bailleul
,
Lennert Jacobs
,
Paolo Manfredi
,
Dries Vande Ginste
,
Marc Moeneclaey
MMSE equalization of multi-Gb/s chip-to-chip interconnects with M-PAM signaling affected by manufacturing tolerances.
SCVT
(2016)