Hao-Yung Lo

Publication Activity (10 Years)

Years Active: 1985-2003
Publications (10 Years): 0

Publications

Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers. J. Electron. Test. 19 (3) (2003)
Hao-Yung Lo
A Parallel CORDIC Algorithm for Sine and Cosine Generation. PDPTA (1997)
Hao-Yung Lo
A Uniform and Squared Direct Two's Complement Multiplier. J. Inf. Sci. Eng. 13 (1) (1997)
Hao-Yung Lo, Hsiu-Feng Lin, Yue-Yuan Ho
Logarithmic Conversion by Four Partitioned Hybrid-ROMs. ISPAN (1996)
Hao-Yung Lo, Hsiu-Feng Lin, Kuen-Shiuh Yang
A New Method of Implementation of VLSI CORDIC for Sine and Cosine Computation. ISCAS (1995)
Hao-Yung Lo
An Optimal Matched and Parallel Mixed-Radix Converter. J. Inf. Sci. Eng. 10 (3) (1994)
Hao-Yung Lo, Hsiu-Feng Lin, Chiang-Shiang Wan
Hybrid ROM Strategy (H-ROM) for Conversion Between Binary Numbers and Logarithms. J. Inf. Sci. Eng. 10 (1) (1994)
Chien-Chun Su, Hao-Yung Lo
An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems. IEEE Trans. Computers 39 (8) (1990)
Hao-Yung Lo
High-speed signed digital multipiers for VLSI. Microprocessing and Microprogramming 29 (4) (1990)
Hao-Yung Lo, Jau-Ling Chen
by Iteration. IEEE Trans. Computers 36 (11) (1987)
Hao-Yung Lo, Yoshinao Aoki
Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array. IEEE Trans. Computers 34 (8) (1985)