Farnaz Mounes-Toussi

Publication Activity (10 Years)

Years Active: 1994-2001
Publications (10 Years): 0

Publications

Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. IEEE J. Solid State Circuits 36 (10) (2001)
J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak
SOI Implementation of a 64-Bit Adder. ICCD (1999)
Farnaz Mounes-Toussi, David J. Lilja
The Effect of using State-Based Priority Information in a Shared-Memory Multiprocessor Cache Replacement Policy. ICPP (1998)
Farnaz Mounes-Toussi, David J. Lilja
The Potential of Compile-Time Analysis to Adapt the Cache Coherence Enforcement Strategy to the Data Sharing Characteristics. IEEE Trans. Parallel Distributed Syst. 6 (5) (1995)
Farnaz Mounes-Toussi, David J. Lilja
Write buffer design for cache-coherent shared-memory multiprocessors. ICCD (1995)
Farnaz Mounes-Toussi, David J. Lilja, Zhiyuan Li
An evaluation of a compiler optimization for improving the performance of a coherence directory. International Conference on Supercomputing (1994)
Trung N. Nguyen, Farnaz Mounes-Toussi, David J. Lilja, Zhiyuan Li
A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement. IFIP PACT (1994)