Erdal Oruklu

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 17

Top Topics

Fpga Implementation

Binary Classification

Convolutional Neural Networks

Top Venues

J. Signal Process. Syst.

J. Comput. Lang.

Publications

Yu Yuan, Kushal Virupakshappa, Erdal Oruklu
Accelerating a Meta Learning Model for Ultrasonic Non-Destructive Testing Applications Using Model Compression and FPGA Hardware. J. Signal Process. Syst. 96 (1) (2024)
Yu Yuan, Kushal Virupakshappa, Erdal Oruklu
Hardware Efficient Implementation of an Ultrasonic Non-Destructive Evaluation Algorithm based on DeepLearning. MWSCAS (2022)
Yu Yuan, Kushal Virupakshappa, Erdal Oruklu
FPGA Implementation of an Ultrasonic Flaw Detection Algorithm Based on Convolutional Neural Networks. J. Signal Process. Syst. 94 (12) (2022)
David Hentrich, Erdal Oruklu, Jafar Saniie
Program diagramming and fundamental programming patterns for a polymorphic computing dataflow processor. J. Comput. Lang. 65 (2021)
David Hentrich, Erdal Oruklu, Jafar Saniie
Fine-Grained Instruction Placement in Polymorphic Computing Architectures. ISCAS (2020)
Caterina Lazaro Martinez, Erdal Oruklu, Mudassir M. Rashid, Mert Sevil, Iman Hajizadeh, Ali Cinar, Jeremy R. Hajek
From Design to Implementation - Algorithm Conversion and Transition to a Mobile Platform for an Artificial Pancreas. SIGITE (2019)
Kushal Virupakshappa, Erdal Oruklu
Investigation of Feature Inputs for Binary Classification of Ultrasonic NDT Signals using SVM and Neural Networks. MWSCAS (2019)
Kangqi Chen, Erdal Oruklu
Side-Channel Attack Resilient Design of a 10T SRAM Cell in 7nm FinFET Technology. MWSCAS (2019)
David Hentrich, Erdal Oruklu, Jafar Saniie
A Dataflow Processor as the Basis of a Tiled Polymorphic Computing Architecture with Fine-Grain Instruction Migration. IEEE Trans. Parallel Distributed Syst. 29 (10) (2018)
Muyu Yang, Erdal Oruklu
Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode. MWSCAS (2018)
Caterina Lazaro Martinez, Erdal Oruklu, Ali Cinar
Security challenges and solutions for closed-loop artificial pancreas systems. MWSCAS (2017)
Yan Han, Erdal Oruklu
Traffic sign recognition based on the NVIDIA Jetson TX1 embedded system using convolutional neural networks. MWSCAS (2017)
Yiyue Jiang, Kushal Virupakshappa, Erdal Oruklu
FPGA implementation of a support vector machine classifier for Ultrasonic flaw detection. MWSCAS (2017)
Caterina Lazaro Martinez, Erdal Oruklu, Mert Sevil, Kamuran Turksoy, Ali Cinar
Hardware and Software Implementation of an Artificial Pancreas System on a Mobile Device. IJHCR 8 (1) (2017)
Yu Yuan, Erdal Oruklu
Leakage reduction techniques for FinFET datapath circuits. EIT (2016)
Caterina Lazaro Martinez, Erdal Oruklu, Mert Sevil, Kamuran Turksoy, Ali Cinar
Communication challenges in a multi-sensor closed-loop artificial pancreas system. Wireless Health (2016)
Caterina Lazaro Martinez, Erdal Oruklu, Mert Sevil, Kamuran Turksoy, Ali Cinar
Implementation of an artificial pancreas system on a mobile device. EIT (2016)
Yu Yuan, Cecilia García Martin, Erdal Oruklu
Standard cell library characterization for FinFET transistors using BSIM-CMG models. EIT (2015)
Caterina Lazaro Martinez, Erdal Oruklu, Ali Cinar
Sensor fusion and distributed platform development for artificial pancreas. EIT (2015)
Kushal Virupakshappa, Yan Han, Erdal Oruklu
Traffic sign recognition based on prevailing bag of visual words representation on feature descriptors. EIT (2015)
Caterina Lazaro Martinez, Erdal Oruklu, Ali Cinar
Cyber-Physical Platform Development for Multivariable Artificial Pancreas Systems. Int. J. Handheld Comput. Res. 6 (3) (2015)
Yan Han, Kushal Virupakshappa, Erdal Oruklu
Robust traffic sign recognition with feature extraction and k-NN classification methods. EIT (2015)
Neelam Patil, Cecilia García Martin, Erdal Oruklu
Performance evaluation of multi-gate fets using the BSIM-CMG model. EIT (2014)
Yan Han, Erdal Oruklu
Real-time traffic sign recognition based on Zynq FPGA and ARM SoCs. EIT (2014)
Cecilia García Martin, Erdal Oruklu
Leakage power reduction in data driven dynamic logic circuits. EIT (2014)
Cecilia García Martin, Erdal Oruklu
Performance evaluation of FinFET pass-transistor full adders with BSIM-CMG model. MWSCAS (2014)
Juan Lu, Erdal Oruklu, Jafar Saniie
Improved time-frequency distribution using singular value decomposition of Choi-Williams distribution. EIT (2013)
Cecilia García Martin, Nicolas Bessou, Anne Chadoeuf, Erdal Oruklu
Image processing design flow for virtual fitting room applications used in mobile devices. EIT (2012)
Tom Chu, Jafar Saniie, Erdal Oruklu
Acoustic sensor array for determination of undersea acoustic signatures. EIT (2012)
Erdal Oruklu, Joshua Weber, Jafar Saniie
System-on-Chip Subband Decomposition Architectures for Ultrasonic Detection Applications. J. Signal Process. Syst. 68 (3) (2012)
Christophe Desmouliers, Erdal Oruklu, Semih Aslan, Jafar Saniie, Fernando Martinez-Vallina
Image and video processing platform for field programmable gate arrays using a high-level synthesis. IET Comput. Digit. Tech. 6 (6) (2012)
Weidi Jia, Won-Jae Yi, Jafar Saniie, Erdal Oruklu
3D image reconstruction and human body tracking using stereo vision and Kinect technology. EIT (2012)
Vijay Anand, Jafar Saniie, Erdal Oruklu
Security Policy Management Process within Six Sigma Framework. J. Information Security 3 (1) (2012)
Erdal Oruklu, Xin Xiao, Jafar Saniie
Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors. J. Signal Process. Syst. 66 (2) (2012)
Semih Aslan, Erdal Oruklu, Jafar Saniie
A high-level synthesis and verification tool for fixed to floating point conversion. MWSCAS (2012)
Erdal Oruklu, Damien Pesty, Joana Neveux, Jean-Emmanuel Guebey
Real-time traffic sign detection and recognition for in-car driver assistance systems. MWSCAS (2012)
David Hentrich, Erdal Oruklu, Jafar Saniie
Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture. Circuits Syst. 2 (4) (2011)
Christophe Desmouliers, Erdal Oruklu, Jafar Saniie
Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s. IET Circuits Devices Syst. 5 (4) (2011)
Jeff Rebacz, Erdal Oruklu, Jafar Saniie
Fast Signed-Digit Multi-operand Decimal Adders. Circuits Syst. 2 (3) (2011)
Vijay Anand, Jafar Saniie, Erdal Oruklu
Trusted computing architectures for a mobile IT infrastructure. SIGUCCS (2011)
Vitaliy Kunin, Marcos Turqueti, Jafar Saniie, Erdal Oruklu
Direction of Arrival Estimation and Localization Using Acoustic Sensor Arrays. J. Sens. Technol. 1 (3) (2011)
Joshua Weber, Erdal Oruklu, Jafar Saniie
FPGA-Based Configurable Frequency-Diverse Ultrasonic Target-Detection System. IEEE Trans. Ind. Electron. 58 (3) (2011)
Xin Xiao, Erdal Oruklu, Jafar Saniie
Reduced memory architecture for CORDIC-based FFT. ISCAS (2010)
Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie
Constant addition with flagged binary adder architectures. Integr. 43 (3) (2010)
Jeff Rebacz, Erdal Oruklu, Jafar Saniie
High performance signed-digit decimal adders. EIT (2009)
Erdal Oruklu, Jafar Saniie
Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging. IEEE Trans. Instrum. Meas. 58 (8) (2009)
Xin Xiao, Erdal Oruklu, Jafar Saniie
Fast memory addressing scheme for radix-4 FFT implementation. EIT (2009)
Christophe Desmouliers, Erdal Oruklu, Jafar Saniie
FPGA-based design of a high-performance and modular video processing platform. EIT (2009)
Semih Aslan, Erdal Oruklu, Jafar Saniie
Realization of area efficient QR factorization using unified division, square root, and inverse square root hardware. EIT (2009)
David Hentrich, Erdal Oruklu, Jafar Saniie
Performance evaluation of SRAM cells in 22nm predictive CMOS technology. EIT (2009)
Yufeng Lu, Erdal Oruklu, Jafar Saniie
Fast Chirplet Transform With FPGA-Based Implementation. IEEE Signal Process. Lett. 15 (2008)
Christophe Desmouliers, Erdal Oruklu, Jafar Saniie
Universal Wavelet Kernel Implementation Using Reconfigurable Hardware. ReConFig (2008)
Yufeng Lu, Erdal Oruklu, Jafar Saniie
Fpga-based hardware/software co-design for chirplet signal decomposition. ACM Great Lakes Symposium on VLSI (2008)
Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie
Performance analysis of flagged prefix adders with logical effort. ISCAS (2008)
Xin Xiao, Erdal Oruklu, Jafar Saniie
An Efficient FFT Engine With Reduced Addressing Logic. IEEE Trans. Circuits Syst. II Express Briefs (11) (2008)
John Moskal, Erdal Oruklu, Jafar Saniie
Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder. ISCAS (2007)
Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie
Design and Synthesis of a Three Input Flagged Prefix Adder. ISCAS (2007)
Erdal Oruklu, Guilherme Cardoso, Jafar Saniie
Reconfigurable architecture for ultrasonic signal compression and target detection. ICASSP (5) (2005)
Erdal Oruklu, Jafar Saniie
Multiplierless architectures for frequency-diverse target detection algorithms. Circuits, Signals, and Systems (2004)