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Dae Hyun Kim
ORCID
Publication Activity (10 Years)
Years Active: 2018-2024
Publications (10 Years): 8
Top Topics
Efficient Optimization
Steiner Tree
Vlsi Design
Hw Sw
Top Venues
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
ACM Trans. Design Autom. Electr. Syst.
IEEE Trans. Emerg. Top. Comput.
AAAI
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Publications
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Monzurul Islam Dewan
,
Sheng-En David Lin
,
Dae Hyun Kim
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing.
ACM Trans. Design Autom. Electr. Syst.
29 (1) (2024)
Aryan Deshwal
,
Syrine Belakaria
,
Janardhan Rao Doppa
,
Dae Hyun Kim
Bayesian Optimization over Permutation Spaces.
AAAI
(2022)
Monzurul Islam Dewan
,
Dae Hyun Kim
Design Automation Algorithms for the NP-Separate VLSI Design Methodology.
ACM Trans. Design Autom. Electr. Syst.
27 (5) (2022)
Sheng-En David Lin
,
Dae Hyun Kim
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
39 (6) (2020)
Monzurul Islam Dewan
,
Dae Hyun Kim
NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
39 (12) (2020)
Sheng-En David Lin
,
Dae Hyun Kim
Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs.
IEEE Trans. Emerg. Top. Comput.
7 (2) (2019)
Sheng-En David Lin
,
Dae Hyun Kim
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
37 (4) (2018)
Inki Hong
,
Dae Hyun Kim
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
37 (8) (2018)