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Chi-Lun Lo
Publication Activity (10 Years)
Years Active: 2011-2017
Publications (10 Years): 5
Top Topics
Analog To Digital Converter
Cmos Image Sensor
Lower Cost
Dynamic Range
Top Venues
IEEE J. Solid State Circuits
VLSIC
ISSCC
Symmetry
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Publications
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Chi-Lun Lo
,
Chi-Hua Chen
,
Ta-Sheng Kuan
,
Kuen-Rong Lo
,
Hsun-Jung Cho
Fuel Consumption Estimation System and Method with Lower Cost.
Symmetry
9 (7) (2017)
Chi-Lun Lo
,
Chi-Hua Chen
,
Jin-Li Hu
,
Kuen-Rong Lo
,
Hsun-Jung Cho
A Fuel-Efficient Route Plan App Based on Game Theory.
IoTaaS
(2017)
Chen-Yen Ho
,
Cong Liu
,
Chi-Lun Lo
,
Hung-Chieh Tsai
,
Tze-Chien Wang
,
Yu-Hsin Lin
15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation.
ISSCC
(2015)
Stacy Ho
,
Chi-Lun Lo
,
Jiayun Ru
,
Jialin Zhao
A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS.
IEEE J. Solid State Circuits
50 (4) (2015)
Chen-Yen Ho
,
Cong Liu
,
Chi-Lun Lo
,
Hung-Chieh Tsai
,
Tze-Chien Wang
,
Yu-Hsin Lin
A 4.5 mW CT Self-Coupled ΔΣ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation.
IEEE J. Solid State Circuits
50 (12) (2015)
Stacy Ho
,
Chi-Lun Lo
,
Zhiyu Ru
,
Jialin Zhao
A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS.
VLSIC
(2014)
Hung-Chieh Tsai
,
Chi-Lun Lo
,
Chen-Yen Ho
,
Yu-Hsin Lin
A 64-fJ/Conv.-Step Continuous-Time Sigma Delta Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital Delta Sigma Truncator.
IEEE J. Solid State Circuits
48 (11) (2013)
Chia-Hsin Wu
,
Wen-Chieh Tsai
,
Chun-Geik Tan
,
Chun-Nan Chen
,
Kuan-I Li
,
Jui-Lin Hsu
,
Chi-Lun Lo
,
Hsin-Hua Chen
,
Sheng-Yuan Su
,
Kun-Tso Chen
,
Min Chen
,
Osama Shana'a
,
Shu-Hung Chou
,
George Chien
A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS.
ISSCC
(2011)