Anuradha Agarwal

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 2

Top Topics

Power Consumption

Boolean Formula

Binary Decision Diagrams

Top Venues

Publications

Francesco Zanetto, Katherine Stoll, Samuel Serna, Anuradha Agarwal, Marco Sampietro, Giorgio Ferrari
6-channel CMOS-based instrument for optical absorption spectroscopy and chemical identification. ISCAS (2023)
Ozan Yakar, Yuqi Nie, Kazumi Wada, Anuradha Agarwal, Ilke Ercan
Energy Efficiency of Microring Resonator (MRR)-Based Binary Decision Diagram (BDD) Circuits. ICRC (2019)
Anuradha Agarwal, Ranga Vemuri
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ICCD (2005)
Huiying Yang, Anuradha Agarwal, Ranga Vemuri
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. ISVLSI (2005)
Anuradha Agarwal, Ranga Vemuri
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. ICCAD (2005)
Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. ACM Great Lakes Symposium on VLSI (2005)
Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ACM Great Lakes Symposium on VLSI (2004)
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
Accurate Estimation of Parasitic Capacitances in Analog Circuits. DATE (2004)
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
Fast and accurate parasitic capacitance models for layout-aware. DAC (2004)
Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE (2004)