Ahmad A. Hiasat

Publication Activity (10 Years)

Years Active: 1995-2022
Publications (10 Years): 13

Top Topics

Processing Units

Top Venues

IEEE Trans. Computers

J. Circuits Syst. Comput.

IEEE Trans. Circuits Syst. I Regul. Pap.

Comput. Electr. Eng.

Publications

Ahmad A. Hiasat
An arithmetic scaler circuit design for the expanded four-moduli set {2k-1, 2k+1, 22k+1, 22k}. Comput. Electr. Eng. 101 (2022)
Ahmad A. Hiasat
A Scaler Design for the RNS Three-Moduli Set {2n+1-1, 2n, 2n-1} Based on Mixed-Radix Conversion. J. Circuits Syst. Comput. 29 (3) (2020)
Ahmad A. Hiasat
A Residue-to-Binary Converter with an Adjustable Structure for an Extended RNS Three-Moduli Set. J. Circuits Syst. Comput. 28 (8) (2019)
Ahmad A. Hiasat, Leonel Sousa
On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2n+k, 2n - 1, 2n+1 - 1}. Comput. J. 62 (2) (2019)
Ahmad A. Hiasat, Leonel Sousa
Sign Identifier for the Enhanced Three Moduli Set {2 n + k , 2 n - 1, 2 n+ 1 - 1}. J. Signal Process. Syst. 91 (8) (2019)
Ahmad A. Hiasat
General modular adder designs for residue number system applications. IET Circuits Devices Syst. 12 (4) (2018)
Ahmad A. Hiasat
- 1}. Comput. 7 (3) (2018)
Ahmad A. Hiasat
}. IET Comput. Digit. Tech. 12 (2) (2018)
Ahmad A. Hiasat
An Efficient Reverse Converter for the Three-Moduli Set ( $ 2^{n+1}-1, 2^{n}, 2^{n}-1$ ). IEEE Trans. Circuits Syst. II Express Briefs (8) (2017)
Ahmad A. Hiasat
A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2017)
Ahmad A. Hiasat
}. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Ahmad A. Hiasat
+1). IEEE Trans. Computers 66 (7) (2017)
Ahmad A. Hiasat
A Sign Detector for a Group of Three-Moduli Sets. IEEE Trans. Computers 65 (12) (2016)
Ahmad A. Hiasat
VLSI implementation of new arithmetic residue to binary decoders. IEEE Trans. Very Large Scale Integr. Syst. 13 (1) (2005)
Omar Hasan, Ahmad A. Hiasat
Limiter discriminator detection of narrow-band duobinary FSK in a land mobile channel. Int. J. Commun. Syst. 17 (1) (2004)
Ahmad A. Hiasat
[plusmn] 1)). Comput. J. 47 (1) (2004)
Ahmad A. Hiasat
A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. Int. J. Comput. Their Appl. 11 (2) (2004)
Ahmad A. Hiasat
An arithmetic residue to binary conversion technique. Integr. 36 (1-2) (2003)
Ahmad A. Hiasat, Omar Hasan
Bit-serial architecture for rank order and stack filters. Integr. 36 (1-2) (2003)
Ahmad A. Hiasat, Andraos Sweidan
+1). J. Syst. Archit. 49 (1-2) (2003)
Ahmad A. Hiasat
High-Speed and Reduced-Area Modular Adder Structures for RNS. IEEE Trans. Computers 51 (1) (2002)
Andraos Sweidan, Ahmad A. Hiasat
On the Theory of Error Control Based on Moduli with Common Factors. Reliab. Comput. 7 (3) (2001)
Ahmad A. Hiasat
Semi-custom VLSI chip implementation of a new two-dimensional separable median filtering algorithm. ICECS (2001)
Ahmad A. Hiasat
New Efficient Structure for a Modular Multiplier for RNS. IEEE Trans. Computers 49 (2) (2000)
Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm. Comput. J. 42 (3) (1999)
Ahmad A. Hiasat
Full-custom VLSI design of a new high-speed modular adder structures. ICECS (1999)
Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
Design and Implementation of An RNS Division Algorithmm. IEEE Symposium on Computer Arithmetic (1997)
Ahmad A. Hiasat
Semi-custom VLSI design for RNS multipliers using combinational logic approach. ICECS (1996)
Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
High-Speed Division Algorithm for Residue Number System. ISCAS (1995)