Aakash Patil

Publication Activity (10 Years)

Years Active: 2015-2021
Publications (10 Years): 12

Top Topics

Feature Extractors

Detecting Anomalies

Neuronal Networks

Image Recognition

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Vivek Saraswat, Ajinkya Gorad, Anand Naik, Aakash Patil, Udayan Ganguly
Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification. CoRR (2021)
Vivek Saraswat, Ajinkya Gorad, Anand Naik, Aakash Patil, Udayan Ganguly
Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification. IJCNN (2021)
Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu
ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2020)
Yi Chen, Zheng Wang, Aakash Patil, Arindam Basu
A 2.86-TOPS/W Current Mirror Cross-Bar-Based Machine-Learning and Physical Unclonable Function Engine For Internet-of-Things Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Yi Chen, Zheng Wang, Aakash Patil, Arindam Basu
A Current Mirror Cross Bar Based 2.86-TOPS/W Machine Learner and PUF with <2.5% BER in 65nm CMOS for IoT Application. ISCAS (2019)
Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu
ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65nm CMOS. CoRR (2019)
Zheng Wang, Yi Chen, Aakash Patil, Jayasanker Jayabalan, Xueyong Zhang, Chip-Hong Chang, Arindam Basu
Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2018)
Vignesh Mahalingam Suresh, Rishi Sidhu, Prateek Karkare, Aakash Patil, Lei Zhang, Arindam Basu
Powering the IoT through embedded machine learning and LoRa. WF-IoT (2018)
Aakash Patil, Shanlan Shen, Enyi Yao, Arindam Basu
Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition. Neurocomputing 261 (2017)
Zheng Wang, Yi Chen, Aakash Patil, Chip-Hong Chang, Arindam Basu
Current mirror array: A novel lightweight strong PUF topology with enhanced reliability. ISCAS (2017)
Aakash Patil, Shanlan Shen, Enyi Yao, Arindam Basu
Random projection for spike sorting: Decoding neural signals the neural network way. BioCAS (2015)
Aakash Patil, Shanlan Shen, Enyi Yao, Arindam Basu
Hardware Architecture for Large Parallel Array of Random Feature Extractors applied to Image Recognition. CoRR (2015)