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Proceedings of the 10th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2017, Cambridge, MA, USA, October 14-18, 2017
Published in:
NoCArc@MICRO (2017)
Keyphrases
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network on chip
interconnection networks
routing algorithm
network simulator
fault tolerant
data transfer
multi processor
packet switched
multi core processors
parallel algorithm
message passing
parallel computers
parallel architectures
image processing
data access
single processor