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Overview
- hybrid method
- hidden state
- pairwise
- design space exploration
- scheduling algorithm
Publications
A Hybrid Method for Equivalence Checking Between System Level and RTL.
J. Circuits Syst. Comput.
A Path-Based Equivalence Checking Method Between System Level and RTL Descriptions Using Machine Learning.
J. Circuits Syst. Comput.
DssEC: A Deep State Sequence Based Equivalence Checker.
CSAE
Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress.
CODES+ISSS
Multi-thread Simulation-based Equivalence Checking between SIM and RTI.
CSAE
Validating GCSE in the scheduling of high-level synthesis.
ATS