High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme.
Donghao XiaYuejun ZhangYuanxin TianMengfan XuLiang WenPublished in: Integr. (2024)
Keyphrases
- low power
- logic circuits
- delay insensitive
- high speed
- low power consumption
- low cost
- power consumption
- signal processor
- cmos technology
- flip flops
- vlsi circuits
- power dissipation
- power reduction
- mixed signal
- digital signal processing
- single chip
- asynchronous circuits
- real time
- gate array
- vlsi architecture
- low complexity
- video codec
- ultra low power