A clock gated flip-flop for low power applications in 90 nm CMOS.
Mohamed O. ShakerMagdy A. BayoumiPublished in: ISCAS (2011)
Keyphrases
- low power
- cmos technology
- flip flops
- power consumption
- high speed
- power dissipation
- nm technology
- low voltage
- single chip
- power management
- silicon on insulator
- power saving
- mixed signal
- vlsi circuits
- low cost
- digital signal processing
- real time
- low power consumption
- image sensor
- vlsi architecture
- logic circuits
- power reduction
- gate array
- cmos image sensor