VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network.
Jhing-Fa WangJia-Ching WangAn-Nan SuenChung-Hsien WuFan-Min LiPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2002)
Keyphrases
- vlsi architecture
- neural network
- vlsi implementation
- speech recognizer
- low power
- low complexity
- real time
- speech recognition
- spoken language
- power consumption
- bayesian networks
- maximum likelihood
- low cost
- multi modal
- unsupervised learning
- maximum entropy
- associative memory
- pattern recognition
- broadcast news
- feature extraction
- feature selection