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An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512).
Luigi Dadda
Marco Macchetti
Jeff Owen
Published in:
ACM Great Lakes Symposium on VLSI (2004)
Keyphrases
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hash functions
high speed
design methodology
circuit design
hardware architecture
design process
efficient implementation
hashing algorithm
real time
similarity search
single chip
physical design
application specific
hardware implementation
query processing
chaotic map
data sets