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Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder.
Bruna Garcia
Bianca Silveira
Cláudio Machado Diniz
Daniel Palomino
Guilherme Corrêa
Published in:
LASCAS (2023)
Keyphrases
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hardware design
hardware implementation
fpga hardware
discrete cosine transform
low cost
image compression
low complexity
general purpose
transform domain
block size
field programmable gate array
distributed video coding
scheduling problem
software engineering
frequency domain
parallel architectures