Low power methodology for an ASIC design flow based on high-level synthesis.
Fahad Bin MuslimAffaq QamarLuciano LavagnoPublished in: SoftCOM (2015)
Keyphrases
- low power
- single chip
- high level synthesis
- design methodology
- high speed
- low cost
- low power consumption
- power consumption
- gate array
- logic circuits
- vlsi architecture
- power reduction
- digital signal processing
- cmos technology
- case study
- cmos image sensor
- user interface
- high power
- design space exploration
- vlsi circuits
- application specific
- ultra low power
- design considerations
- mixed signal
- efficient implementation
- general purpose