Login / Signup

Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons.

Sidharth MaheshwariGourav Modi SiddharthaNachiket Kapre
Published in: FPL (2016)
Keyphrases
  • sparse matrix
  • hardware architecture
  • sparse linear
  • random projections
  • field programmable gate array
  • hardware implementation
  • floating point
  • rows and columns
  • signal processing
  • data sets