A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications.
Aniruddha ShastriGreg StittEduardo RiccioPublished in: ASAP (2015)
Keyphrases
- fault tolerant
- high level synthesis
- parallel architecture
- fault tolerance
- distributed systems
- interconnection networks
- hardware implementation
- load balancing
- scheduling algorithm
- low cost
- scheduling problem
- high availability
- state machine
- search algorithm
- optimal solution
- signal processing
- parallel machines
- field programmable gate array
- design space exploration
- parallel processing
- artificial intelligence
- shared memory
- safety critical