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A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter.

Anshul VermaBishnu Prasad Das
Published in: VLSID (2024)
Keyphrases
  • low power
  • power consumption
  • low cost
  • high speed
  • dual band
  • packet loss
  • low power consumption
  • cmos technology
  • logic circuits
  • gate array
  • phase locked loop
  • computer vision
  • feature extraction
  • power dissipation