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Designing efficient accelerator of depthwise separable convolutional neural network on FPGA.
Wei Ding
Zeyu Huang
Zunkai Huang
Li Tian
Hui Wang
Songlin Feng
Published in:
J. Syst. Archit. (2019)
Keyphrases
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convolutional neural network
decision trees
high speed
computationally efficient
cost effective
parallel implementation
real time
databases
information retrieval
information systems
website
support vector machine
signal processing
field programmable gate array