A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse.
Heng LiuLi DingJing JinJianjun ZhouPublished in: ISCAS (2018)
Keyphrases
- low cost
- hardware implementation
- field programmable gate array
- heterogeneous computing
- hardware and software
- reconfigurable architecture
- embedded systems
- real time
- reconfigurable hardware
- hardware architecture
- high speed
- digital signal processor
- computing systems
- general purpose
- learning objects
- efficient implementation
- computer systems
- signal processing
- neural network
- computing power
- image processing
- hardware design
- data acquisition
- vlsi implementation