STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing.
Kejie HuangRong ZhaoYong LianPublished in: NANOARCH (2014)
Keyphrases
- low power
- logic circuits
- high speed
- low cost
- power consumption
- random access memory
- delay insensitive
- asynchronous circuits
- single chip
- design considerations
- high power
- digital signal processing
- wireless transmission
- data storage
- vlsi architecture
- file system
- power reduction
- gate array
- low power consumption
- mixed signal
- main memory
- ultra low power
- vlsi circuits
- image sensor
- database management systems