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The Case for Hard Matrix Multiplier Blocks in an FPGA.

Aman AroraZhigang WeiLizy K. John
Published in: FPGA (2020)
Keyphrases
  • hardware implementation
  • high speed
  • real time
  • real time image processing
  • rows and columns
  • objective function
  • pairwise
  • denoising
  • software implementation
  • parallel hardware